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AltiVec Extension to PowerPC Accelerates Media Processing: IEEE Micro, Vol. 20, No. 2. (March 2000), pp. 85-95.There is a clear trend in personal computing toward multimedia-ric h applications. These applications will incorporate a wide variety of multimedia technologies, including audio and video compression, 2D image processing, 3D graphics, speech and handwriting recognition, media mining, and narrow/broadba nd signal processing for communication. In response to this demand, major microprocessor vendors have announced architectural extensions to their general-purpos e processors in an effort to improve their multimedia performance. Intel extended IA-32 with MMX and SSE (alias KNI), Sun enhanced Sparc with VIS, Hewlett-Packar d added MAX to its PA-RISC architecture, Silicon Graphics extended the MIPS architecture with MDMX, and Digital (now Compaq) added MVI to Alpha. This article describes the most recent, and what we believe to be the most comprehensive, addition to this list: PowerPC's AltiVec, AltiVec speeds not only media processing but also nearly any application in which data parallelism exists, as demonstrated by a cycle-accurate simulation of Motorola's MPC 7400, the heart of Apple G4 systemsKeith Diefendorff, Pradeep Dubey, Ron Hochsprung, Hunter Scales

Source: IEEE Micro, Vol. 20, No. 2. (March 2000), pp. 85-95.
Strength Reduction of Integer Division and Modulo Operations: Languages and Compilers for Parallel Computing (2003), pp. 1-14.Integer division, modulo, and remainder operations are expressive and useful operations. They are logical candidates to express complex data accesses such as the wrap-around behavior in queues using ring buffers. In addition, they appear frequently in address computations as a result of compiler optimizations that improve data locality, perform data distribution, or enable parallelizatio n. Experienced application programmers, however, avoid them because they are slow. Furthermore, while advances in both hardware and software have improved the performance of many parts of a program, few are applicable to division and modulo operations. This trend makes these operations increasingly detrimental to program performance. This paper describes a suite of optimizations for eliminating division, modulo, and remainder operations from programs. These techniques are analogous to strength reduction techniques used for multiplication s. In addition to some algebraic simplification s, we present a set of optimization techniques that eliminates division and modulo operations that are functions of loop induction variables and loop constants. The optimizations rely on algebra, integer programming, and loop transformation s.Jeffrey Sheldon, Walter Lee, Ben Greenwald, Saman Amarasinghe

Source: Languages and Compilers for Parallel Computing (2003), pp. 1-14.
New microarchitect ure challenges in the coming generations of CMOS process technologies (keynote address)(abstr act only): (1999)Fred Pollack

Source: (1999)
Mechanisms for store-wait-fre e multiprocessor s: SIGARCH Comput. Archit. News, Vol. 35, No. 2. (May 2007), pp. 266-277.Thomas Wenisch, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos

Source: SIGARCH Comput. Archit. News, Vol. 35, No. 2. (May 2007), pp. 266-277.
Shared Memory Consistency Models: A Tutorial: Computer, Vol. 29, No. 12. (December 1996), pp. 66-76.Sarita Adve, Kourosh Gharachorloo

Source: Computer, Vol. 29, No. 12. (December 1996), pp. 66-76.
Characterizing Logical Masking Of Transient Faults At The Microarchitect ural And Architectural Levels: In this work, the e#ects of transient faults on high performance microprocessor s is explored. To perform a thorough exploration, a highly detailed RTL model of a modern, deeply pipelined, out-of-order microprocessor implementing the Alpha ISA was created. Using this model, the e#ects of manipulating individual state elements such as pipeline latches and RAM cells can be observed by comparing the results against that of a reference simulation. Using statistical fault injection into our...Nicholas Wang
The case for the reduced instruction set computer: SIGARCH Comput. Archit. News, Vol. 8, No. 6. (October 1980), pp. 25-33.David Patterson, David Ditzel

Source: SIGARCH Comput. Archit. News, Vol. 8, No. 6. (October 1980), pp. 25-33.
Reflections on the memory wall: (2004)This paper looks at the evolution of the "Memory Wall" problem over the past decade. It begins by reviewing the short Computer Architecture News note that coined the phrase, including the motivation behind the note, the context in which it was written, and the controversy it sparked. What has changed over the years? Are we hitting the Memory Wall? And if so, for what types of applications?S ally Mckee

Source: (2004)
Can programming be liberated from the von Neumann style?: a functional style and its algebra of programs: Commun. ACM, Vol. 21, No. 8. (August 1978), pp. 613-641.John Backus

Source: Commun. ACM, Vol. 21, No. 8. (August 1978), pp. 613-641.

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